Conventional read/write memories, for example static random access memories (SRAMs), as are commonly used in computer systems lose their stored information when power is removed from the device. Thus, a computer system which has only read/write memory will lose all of its stored information if power is removed or temporarily lost. Accordingly, computer system designers have recognized the need to back up information stored in volatile memories in the event that power is lost, e.g., during a blackout or brownout.
One way to back up a volatile memory such as an SRAM is to transfer the data stored in the SRAM to a separate non-volatile memory before the power is turned off or is about to fail. Unfortunately, such a solution requires that the data be transferred bit-by-bit between the volatile memory and the non-volatile memory. Such a data transfer, which typically occurs over a slow, serial link, cannot accommodate the large amounts of data stored in modern SRAMs (e.g., of the order of 14 Mbits) before a complete failure of power.
Recognizing that the serial transfer of data between volatile and non-volatile devices is not an acceptable solution, memory designers have attempted to incorporate non-volatile storage devices within conventional SRAM architectures. In this way, the memory circuits operate in the conventional manner during usual operation but, upon an appropriate command, the data state stored in the volatile memory cells of the device can be transferred to the non-volatile storage elements of the device. When power is restored, this data state can be returned to the volatile memory elements.
Although the combination of volatile and non-volatile memory elements within the same device has been attempted, the solutions of the past tend to produce memory cells having a substantially increased area configuration. For example, memory devices such as that shown in FIG. 1 have attempted to integrate non-volatile storage elements with conventional six transistor (6T) or four transistor (4T) SRAMs. FIG. 1 illustrates a non-volatile SRAM (NVSRAM) 10 that includes a volatile storage portion 12 and a nonvolatile storage portion 14. Volatile storage portion 12 is a conventional 2T-2R SRAM cell which includes resistors 16 and 18 and N-channel transistors 20 and 22. When coupled together as shown in FIG. 1, resistor-transistor pairs 16 and 20, and 18 and 22 act as latches to store a logic state of SRAM cell 10. Volatile storage portion 12 is coupled between a pair of bit lines, BL and BL, through a pair of select transistors 24 and 26. Select transistors 24 and 26 couple volatile storage portion 12 to the bit lines BL and BL in response to control signals from word line WL.
Coupled to volatile storage portion 12 is non-volatile storage portion 14. Non-volatile storage portion 14 includes SONOS cells 28-34 and select transistors 36 and 38. SONOS cells 28-34 are non-volatile storage elements which use a nitride floating gate. In response to a programming voltage (Vpas) applied to a control line 40, SONOS cells 30 and 34 capture the logic state of volatile storage portion 12. This state is retained by SONOS cells 28-34 even if power is removed from memory cell 10. To recall the state, for example upon power up, a recall voltage (Vrcl) is applied to control line 42. This has the effect of restoring the stored state of memory cell 10 to the volatile storage portion 12. Non-volatile storage portion 14 is coupled into and/or out of memory cell 10 in response to a select voltage (Vse) applied to control line 44.
NVSRAM cell 10 is very large (in terms of die area) as compared to a conventional SRAM cell (e.g., a conventional 6T cell). In particular, six additional elements, SONOS cells 28-34 and pass gates 36 and 38, as well as three additional control lines, 40-44, are added to a conventional SRAM cell. Further, SONOS cells 28-34 require specifically timed to properly store and recall the state of memory cell 10. Thus, in addition to requiring complex pulses on control lines 40-44 for non-volatile operation, such a cell requires increased die area and, for a given size die, will reduce the density of available storage cells. It would be desirable to have a non-volatile SRAM cell which does not require the significantly increased die area and/or control pulses of such cells of the past.